VLSI System Design- FREQUENTLY ASKED QUESTIONS

1.Explain how logical gates are controlled by Boolean logic?

In Boolean algebra, the true state is denoted by the number one, referred as logic one or logic high. While, the false state is represented by the number zero, called logic zero or logic low. And in the digital electronic, the logic high is denoted by the presence of a voltage potential.

• NOT Gate: It has one out input and one output. For example, if the value of A= 0 then the Value of B=1 and vice versa
• AND Gate: It has one output due to the combination of two output. For example, if the value of A and B= 1 then value of Q should be 1
• OR Gate: Either of the value will show the same output. For example, if the value of A is 1 or B is 0 then value of Q is 1
These are the basic three types of gates where Boolean logic work, apart from these, other gates that are functional works with the combination of these three basic gates, they are XNOR gate, NAND gate, Nor gate and XOR gate.

2.Explain Verilog?

Verilog is an HDL (Hardware Description Language) for describing electronic circuits and systems. In Verilog, circuit components are prepared inside a Module. It contains both behavioral and structural statements. Structural statements signify circuit components like logic gates, counters and micro-processors. Behavioral statements represent programming aspects like loops, if-then statements and stimulus vectors.
Verilog can be different to normal programming language in following aspects;
• Simulation time concept
• Multiple threads
• Basic circuit concepts like primitive gates and network connections

3. What is the purpose of having Depletion mode Device?

Depletion modes are used in MOSFET it is a device that remains ON at zero gate-source voltage. This device consists of load resistors that are used in the logic circuits. This types are used in N-type depletion-load devices that allow the threshold voltages to be taken and use of -3 V to +3V is done. The drain is more positive in this comparison of PMOS where the polarities gets reversed. The mode is usually determined by the sign of threshold voltage for N-type channel. Depletion mode is the positive one and used in many technologies to represent the actual logic circuit. It defines the logic family that is dependent on the silicon VLSI. This consists of pull-down switches and loads for pull-ups.

4. Explain why present VLSI circuits use MOSFETs instead of BJTs?

In comparison to BJT, MOSFETS can be made very compact as they occupy very small silicon area on IC chip and also in term of manufacturing they are relatively simple. Moreover, digital and memory ICs can be employed with circuits that use only MOSFETs, i.e., diodes, resistors, etc.CMOS technology allows the power dissipation to be low and it gives more power output, whereas bipolar takes lots of power to run the system and the circuitry require lots of power to get activated. CMOS technology provides high input impedance that is low drive current that allow more current to be flown in the circuit and keep the circuit in a good position, whereas it provides high drive current means more input impedance.

5. Explain what is a sequential circuit?

A sequential circuit is a logical circuit, where the output depends on the present value of the input signal as well as the sequence of past inputs. While a combinational circuit is a function of present input only. A sequential circuit is a combination of combinational circuit and a storage element. the sequential circuits use current input variables and previous input variables which are stored and provides the data to the circuit on the next clock cycle.

The sequential circuits are classified into two types;
• Synchronous Circuit
• Asynchronous Circuit
In synchronous sequential circuits, the state of device changes at discrete times in response to a clock signal. In asynchronous circuits, the state of the device changes in response to changing inputs

6.What is latch-up in CMOS and how it can be avoided?

• Latch is the generation of a low-impedance path in CMOS chips between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs for a silicon-controlled rectifier with positive feedback and virtually short circuit the power and the ground rail.
• This causes excessive current flows and potential permanent damage to the devices.
To avoid latch-up
• Reduce the BJT gains by lowering the minority carrier lifetime through Gold doping of the substrate (solution might cause excessive leakage currents).
• Use p+ guard band rings connected to ground around nMOS transistors and n+ guard rings connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected minority carriers before they reach the base of the parasitic BJT.
• Place substrate and well contacts as close as possible to the source connections of the MOS transistors to reduce the values of Rw and Rsub

7.Explain what is VHDL

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language. VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.
VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected

8. What is the difference between simulation and synthesis?

Simulation
Is used to verify the functionality of the circuit.
a)Functional Simulation: study of ckt’s operation independent of timing parameters and gate delays.
b) Timing Simulation: study including estimated delays, verify setup, hold and other timing requirements of devices like flip flops are met.

Synthesis
One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives or components(as in FPGA’S) to fit into the target technology. Basically the synthesis tools convert the design description into equations or components

9. What is the difference between NMOS and PMOS technologies?

PMOS consists of metal oxide semiconductor that is made on the n-type substrates and consists of active careers named as holes. These holes are used for migration purpose of the charges between the p-type and the drain. Whereas, NMOS consists of the metal oxide semiconductor and they are made on p-type substrates. It consists of electrons as their carriers and migration happens between the n-type source and drain.

On applying the high voltage on the logic gates NMOS will be conducted and will get activated, whereas PMOS require low voltage to be activated.

NMOS are faster than PMOS as the carriers that NMOS uses are electrons that travels faster than holes. The speed is twice as fast as holes.

PMOS are more immune to noise than NMOS.

10. Summary of the different steps in a VLSI Design Flow

VLSI Design Flow

Step 1: Logic Synthesis
• RTL conversion into netlist
• Design partitioning into physical blocks
• Timing margin and timing constrains
• RTL and gate level netlist verification
• Static timing analysis

Step 2: Floor planning
• Hierarchical VLSI blocks placement
• Power and clock planning

Step 3: Synthesis
• Timing constrains and optimization
• Static timing analysis
• Update placement
• Update power and clock planning

Step 4: Block Level Layout
• Complete placement and routing of blocks

Step 5: VLSI Level Layout
• VLSI integration of all blocks
• Place and route
• GDSII creation

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